1. Field of the Invention
The invention relates in general to a flat display substrate, and more particularly to a thin-film transistor liquid crystal display (TFT-LCD) substrate.
2. Description of the Related Art
Thin-film transistor liquid crystal displays (TFT-LCDs) have been applied in the mainstream market nowadays owing to various advantages such as low electricity, small sizes and low radiation rather than cathode ray tubes. But as for the response rate and the reliability of pixels in TFT-LCDs, it is still flawed in a number of ways.
FIG. 1A is a cross-sectional view of a conventional TFT-LCD substrate. Referring to FIG. 1A, a conventional TFT-LCD substrate 100 mainly includes a substrate 110 and a planarization layer 140 disposed thereon. There are a buffer layer 115, a silicon dioxide layer 118, an dielectric layer 130 and a passivation layer 135 in sequence covered on the substrate 110 and the planarization layer 140 further covers thereon.
The substrate 110 is defined to form a thin-film transistor (TFT) 116 and a contact plug 120 thereon. Here, the metal layer where the gate of the TFT 116 located is known as Mantel 1, and the metal layer where the contact plug 120 located is known as Metal 2. The source/drain 125 of the TFT 116 is electrically coupled with the contact plug 120. The passivation layer 135 is disposed on the substrate 110 and the planarization layer 140 is further disposed thereon. The planarization layer 140 and the passivation layer 135 have a via hole 145 for both penetrating the planarization layer 140 and the passivation layer 135 to expose to the contact plug 120. The via hole 145 is sequentially formed with a taper 149 at a lateral view by reflow. After the process of reflow, a dielectric material layer is deposited at the inner surface of the via hole 145 and also deposited within the planarization layer 140 and the passivation layer 135 to form an Indium Tim Oxide (ITO) layer 150. As a result, the ITO layer 150 is electrically coupled with the contact plug 120, shown in FIG. 1A.
FIG. 1B is the cross-sectional view of the via hole in FIG. 1A along the direction 1B–1B′. Referring to FIG. 1B, FIG. 1B shows that the configuration of the cross-section 147 of the via hole 145 is circular shaped but curtails the profile of the ITO layer 150 which is deposited at the inner surface of the via hole 145.
FIG. 1C is an enlarged view of the identified part 1C in FIG. 1A. Referring both to FIG. 1A and FIG. 1C, the gradient of the taper 149 of the via hole 145 is determined in the process of reflow. Conventionally, the resultant taper 149 has a larger gradient, like 75 degrees. The large gradient is mainly caused by the circular configuration of the cross-section 147 of the via hole 145.
Consideration should be given here to the ITO layer 150, deposited at the inner surface of the via hole 145 and also within the planarization layer 140 and the passivation layer 135. There is a sharp-pointed indentation 159 at the junction of the ITO layer 150 and the contact plug 120. As a result, when the ITO layer 150 is deposited at the inner surface of the via hole 145 and also deposited within the planarization layer 140 and over the passivation layer 135, the depth of the ITO layer 150 at the sharp-pointed indentation 159 is thinner than other parts of the ITO layer 150. Consequently, the depth deficiency indicates that the resistance of the sharp-pointed indentation 159 is relatively larger. That is, when depth deficiency occurs, the sharp-pointed indentation 159 has a smaller cross-section area than other parts of the ITO layer 150. Since an element's resistance is inversely proportional to its cross-sectional area, the sharp-pointed indentation 159 has a larger resistance value by series connection. When the pixels of the TFT-LCD are switched on/off by the TFT 116, there is a delay for brightness response of the pixels of the TFT-LCD at the sharp-pointed indentation 159 owing to a relatively larger resistance being electrically connected by series connection therewith, which increases the response time.
Another disadvantage of the sharp-pointed indentation 159 is that the ITO layer 150 may be subject to impacts from external stress and be damaged at the sharp-pointed indentation 159 where the depth deficiency exists. Damage of the ITO layer 150 blocks the electrical coupling so that the pixels of the TFT-LCD can't be driven by the TFT 116. Light spot is consequently generated and the quality of the TFT-LCD is spoiled.
Alternately, a single planarization layer 140 can be substituted for aforesaid the planarization layer 140 and the passivation layer 135 on the contact plug 120. So, the via hole 145 only penetrates the planarization layer 140 and exposes to the contact plug 120. Further, the via hole 145 is sequentially formed with a second taper 149 at a lateral view by reflow. The gradient of the second taper 149 of the via hole 145 here is similar to the foresaid one. In that event, it is understood that the gradient of the taper 149 of the via hole 145 is determined by the shape for the configuration of the via hole 145 rather than what layer, only single planarization layer 140 or both the planarization layer 140 and the passivation layer 135, deposits on the contact plug 120.